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mpq4420 a - aec1 2a, 36v,synchronous step - down converter with pg and ext. sync with force d ccm mode, mpq4420 - aec1 with out force d ccm mode mpq4420 a rev . 1.0 www.monolithicpower.com 1 5/24/2016 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. description the mpq4420a is a high - efficiency , synchronous, rectified, step - down, switch - mode converter with built - in power mosfets. it offers a very compact solution that achieve s 2 a of continuous output current with excellent load and line regulation ove r a wide input supply range. the mpq4420a uses synchronous mode operation to achieve higher efficiency over the output current load range. current - mode operation provides fast transient response and eases loop stabilization. full protection features inclu de over - current protection (ocp) and thermal shutdown. the mpq4420a requires a minimal number of readily available , standard , external components and is available in a compact, 8 - pin , tsot23 package. features ? wide 4v to 36v continuous operating input ra nge ? 90 m/ 55m low r ds(on) internal power mosfets ? high - efficiency synchronous mode operation ? default 4 10 k hz switching frequency ? synchronizes to a 200 k hz to 2 .2 mhz external clock ? high duty cycle for automotive cold crank ? forced ccm ? internal soft start ? power good ? over - current protection ( ocp ) and hiccup ? thermal shutdown ? output adjustable from 0.8v ? available in a tsot23 - 8 package ? available in aec - q100 grade 1 applications ? automotive ? industrial control system ? distributed power systems all mps parts are lead - free, hal ogen - free, and adhere to the rohs directive. for mps green status, please visit the mps website under quality assurance. ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application 22f c1 0.1f c4 22 r4 10h l1 47f c2 41.2k r1 3.3v/2a 13k r2 51k r3 vin en/sync vout sw 3 en/sync 6 in 2 fb 8 vcc 7 bst 5 gnd 4 mpq4420a pg 1 0.1f c3
mpq4420 a ? 2a , 3 6 v, synchronous , step - down converter mpq4420 a rev . 1.0 www.monolithicpower.com 2 5/24/2016 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. ordering information part number* package top marking mpq4420agj tsot23 - 8 see below mpq4420agj - aec1 tsot23 - 8 * for tape & reel, add suffix ? z (e.g. mpq4420agj ? z) top marking apj : product code of mpq4420agj and mpq442 0agj - aec1 y: year code package reference top view tsot23 - 8
mpq4420 a ? 2a , 3 6 v, synchronous , step - down converter mpq4420 a rev . 1.0 www.monolithicpower.com 3 5/24/2016 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. absolute maximum rat ings (1) v in ................................ ................ - 0.3v to 40v v sw ................................................ - 0.3v to 41v v bs ................................ ......................v sw + 6v all other pins ................................ - 0.3v to 6v (2) continuous power dissipation (t a = + 25 c) ( 3 ) tsot23 - 8 ................................................ 1.25w junction temperatu re ............................... 150 c lead temperature ................................ .... 260 c storage temperature .................. - 65 c to 150 c recommended operating conditions continuous supply voltage ( v in ) ......... 4v to 36v output voltage ( v out ) ............... 0.8v to 0.9 x v in operating junction temp . (t j ). .. - 40 c to +125 c thermal resistance ( 4 ) ja jc tsot23 - 8 ............................. 100 ..... 55 ... c/w notes : 1) absolute maximum ratings are rated under room temperature unless otherwise noted. exceeding these ratings may damage the device. 2) for details o n en ? s abs max rating, please refer to the enable/sync c ontrol section on page 14 . 3) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), t he junction - to - ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperat ure is calculated by p d (max) = (t j (max) - t a )/ ja . exceeding the maximum allowable power dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. internal thermal shutdown circuitry protects the device from perm anent damage. 4) measured on jesd51 - 7, 4 - layer pcb.
mpq4420 a ? 2a , 3 6 v, synchronous , step - down converter mpq4420 a rev . 1.0 www.monolithicpower.com 4 5/24/2016 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. electrical character istics v in = 12v, t j = - 40 c to + 1 25 c, unless otherwise noted. typical values are at t j = +2 5 c . parameter symbol condition min typ max units supply current (shutdown ) i shdn v en = 0v 8 a supply current (quiescent ) i q v en = 2v, v fb = 1v , no switching 0. 6 0. 8 ma hs switc h on resistance r on_hs v bst-sw = 5v 90 155 m ls switch on resistance r on_ls v cc = 5v 55 105 m switch leakage i lkg sw v en = 0v, v sw = 12v 1 a current limit i limit under 40% duty cycle 3 .4 5.6 7.8 a oscillator frequency f sw v fb = 750m v 320 410 500 k hz fold back frequency f fb v fb < 400mv 70 1 00 1 30 k hz maximum duty cycle d max v fb = 7 5 0mv , 41 0khz 9 2 9 5 % minimum on time ( 5 ) t o n_ min 70 n s sync frequency ran ge f sync 0.2 2 .4 mhz feedback voltage v fb t j = 25 c 7 80 792 8 04 mv 7 76 8 08 feedback current i fb v fb = 8 2 0mv 10 10 0 na en rising threshold v en rising 1. 15 1.4 1.6 5 v en falling threshold v en_falling 1. 05 1.25 1.4 5 v en threshold hysteresis v en_ hys 150 mv en input current i en v en = 2v 4 6 a v en = 0 0 0.2 a v in under - voltage lockout threshold rising inuv rising 3. 3 3. 5 3. 7 v v in under - voltage lockout threshold falli ng inuv falling 3. 1 3. 3 3. 5 v v in under - voltage lockout threshold hysteresis inuv hys 2 00 mv vcc regulator v cc i cc = 0 ma 4. 6 4.9 5. 2 v vcc load regulation i cc = 5ma 1 .5 4 % soft - start period t ss v out from 10% to 90% 0. 55 1. 45 2.45 ms thermal shutdown ( 5 ) 150 1 7 0 c thermal hysteresis ( 5 ) 3 0 c pg rising threshold pg vth _rising as a percentage of v fb 86 90 9 4 % pg falling threshold pg vth falling as a percentage of v fb 8 0 84 8 8 %
mpq4420 a ? 2a , 3 6 v, synchronous , step - down converter mpq4420 a rev . 1.0 www.monolithicpower.com 5 5/24/2016 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. electrical character istics (continued) v in = 12v, t j = - 40 c to + 1 25 c, unless otherwise noted. typical values are at t j = +2 5 c . parameter symbol condition min typ max units pg threshold hysteresis pg vth _hys as a percentage of v fb 6 % pg rising delay pg td _rising 40 9 0 1 60 s pg falling delay pg td _falling 30 55 95 s pg sink current capability v pg sink 4ma 0.1 0. 3 v pg l eakage current i lkg_pg 10 100 na note : 5) derived from bench characterization. not tested in production .
mpq4420 a ? 2a , 3 6 v, synchronous , step - down converter mpq4420 a rev . 1.0 www.monolithicpower.com 6 5/24/2016 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. typical characteristics
mpq4420 a ? 2a , 3 6 v, synchronous , step - down converter mpq4420 a rev . 1.0 www.monolithicpower.com 7 5/24/2016 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. typical characteristics (continued)
mpq4420 a ? 2a , 3 6 v, synchronous , step - down converter mpq4420 a rev . 1.0 www.monolithicpower.com 8 5/24/2016 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. typical performance characteristics v in = 12v, v out = 3.3v, l = 10h, r bst = 20 , t a = +25c, unless otherwise noted.
mpq4420 a ? 2a , 3 6 v, synchronous , step - down converter mpq4420 a rev . 1.0 www.monolithicpower.com 9 5/24/2016 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. typical performance characteristics (continued) v in = 12v, v out = 3.3v, l = 10h, r bst = 20 , t a = +25c, unless otherwise noted.
mpq4420 a ? 2a , 3 6 v, synchronous , step - down converter mpq4420 a rev . 1.0 www.monolithicpower.com 10 5/24/2016 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. typical performance characteristics (continued) v in = 12v, v out = 3.3v, l = 10h, r bst = 20 , t a = +25c, unless otherwise noted.
mpq4420 a ? 2a , 3 6 v, synchronous , step - down converter mpq4420 a rev . 1.0 www.monolithicpower.com 11 5/24/2016 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. typical performance characteristics (continued) v in = 12v, v out = 3.3v, l = 10h, r bst = 20 , t a = +25c, unless otherwise noted.
mpq4420 a ? 2a , 3 6 v, synchronous , step - down converter mpq4420 a rev . 1.0 www.monolithicpower.com 12 5/24/2016 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. pin functions pin # name description 1 pg power good . the output of pg is an o pen drain and goes high if the output voltage exceeds 90% of the nominal voltage. 2 in supply volt age . the mpq4420a operates from a 4v to 36v input rail. c1 is required to decouple the input rail. connect using a wide pcb trace. 3 sw switch output . conne ct using a wide pcb trace. 4 gnd system ground . gnd is the reference ground of the regulated output voltage . gnd require s special consideration during pcb layout. for best results, connect gnd with copper traces and vias. 5 bst bootstrap. a capacitor con nected between sw and bs t is required to form a floating supply across the high - side switch driver. a 2 0 resistor placed between sw and bst is strongly recommended to reduce sw voltage spike s . 6 en/sync enable/ synchronize . drive en /sync high to enable th e mpq4420a. apply an external clock to en /sync to change the switching frequency. 7 vcc bias supply . decouple vcc with a 0.1 f - to - 0.22 f capacitor. select a capacitor that does not exceed 0.22 f . 8 fb feedback. connect fb to the tap of an external resis tor divider from the output to gnd to set the output voltage. when the fb voltage is below 66 0mv , the frequency foldback comparator lowers the oscillator frequency to prevent current limit runaway during a short - circuit fault condition .
mpq4420 a ? 2a , 3 6 v, synchronous , step - down converter mpq4420 a rev . 1.0 www.monolithicpower.com 13 5/24/2016 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. block diagram f igure 1 : functional block diagram
mpq4420 a ? 2a , 3 6 v, synchronous , step - down converter mpq4420 a rev . 1.0 www.monolithicpower.com 14 5/24/2016 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. operation the mpq4420a is a high - efficiency , synchronous, rectified, step - down, switch - mode converter with built - in power mosfets. it offers a very compact solution that achieve s 2 a of continuous output current with excellent load and line regulation over a wide input supply range. the mpq4420a operates in a fixed - frequency, peak - current - control mode to regulate the output voltage. an internal clock initiates a pwm cycle. the integrated high - side p ower mosfet (hs - fet) turns on and remains on until its current reaches the value set by the comp voltage (v comp ) . when the power switch is off, it remains off until the next clock cycle starts. if the current in the power mosfet does not reach the current value set by comp within 9 5 % of one pwm period, the power mosfet is forced off . internal regulator the 5v internal regulator power s most of the internal circuitries. this regulator takes the v in input and operates in the full v in range . when v in exceeds 5. 0v, the output of the regulator is in full regulation; when v in falls below 5.0v, the output of the regulator decreases following v in . a 0.1 f decoupling ceramic capacitor is needed at vcc . error amplifier (ea) the error amplifier compares the fb voltage a gainst the internal 0.8v reference (ref) and outputs a comp voltage that controls the power mosfet current. the optimized internal compensation network minimizes the external component count and simplifies the control loop design. enable/sync c ontrol en/s y nc is a digital control that turns the regulator on and off . drive en /sync high to turn on the regulator ; drive en/sync low to turn off the regulator . an internal 500k ? resistor from en/ s ync to gnd allows en/ s ync to be floated to shut down the chip. en /sync is clamped internally using a 6. 5 v series zener diode (see figure 2 ) . connect the en /sync input through a pull - up resistor to any voltage connected to v in . the pull - up resistor limits the en /sync input current below 1 5 0 a. for example, with 12v connected to v in , r pullup (12v ? 6. 5 v) 1 5 0 a = 36.7 k? . connecting en /sync directly to a voltage source without a pull - up resis tor requires limiting the voltage amplitude below or equal to 6v to prevent damage to the zener diode. figure 2 : 6.5v - type zener diode to use the synchronous function, c onnect an external clock in the range of 200khz to 2 .2 mhz to en/sync . the external clock should be connected at least 2ms after the output voltage is set . t he internal clock rising edge is synchronized to the external clock rising edge when the external clock is connected . the pulse width of the external clock sign al should be below 1.7s. under - voltage lockout (uvlo) under - voltage lockout (uvlo) protects the chip from operating at an insufficient supply voltage. the mpq4420a ?s uvlo comparator monitors the output voltage of the internal regulator ( vcc ) . the uvlo ris ing threshold is about 3. 5 v , while its falling threshold is 3. 3 v . internal soft start (ss) the soft start (ss) prevents the converter output voltage from overshooting during start - up. when the chip starts up , the internal circuitry generates a soft - start v oltage that ramps up from 0v to 1.2v. when ss is lower than ref, ss overrides ref so the error amplifier uses ss as the reference. when ss exceeds ref, the error amplifier uses ref as the reference. the ss time is internally set to 1.5ms. over - current prot ection (ocp) and hiccup the mpq4420a uses a cycle - by - cycle over - current limit when the inductor current peak value exceeds the set current - limit threshold. if the output voltage drop s until fb is below the under - voltage (uv) threshold ( typically 84 % below the reference ), the mpq4420a enters hiccup mode to restart the part periodically . this protection mode is especially useful when the output is dead- shorted to ground.
mpq4420 a ? 2a , 3 6 v, synchronous , step - down converter mpq4420 a rev . 1.0 www.monolithicpower.com 15 5/24/2016 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. the average short - circuit current is reduced greatly to alleviate thermal iss ues and pro tect the regulator . the mpq4420a exits hiccup mode once the over - current condition is removed. thermal shutdown thermal shutdown prevents the chip from operating at exceedingly high temperatures. when the silicon die temperature exceeds 1 7 0 c, the entire c hip shuts down . when the temperature drops below its lower threshold (typically 1 4 0 c) the chip is enabled again. floating driver and bootstrap charging an external bootstrap capacitor power s the floating power mosfet driver. a dedicated internal regulator charges and regulates the bootstrap capacitor voltage to about 5v ( see figure 3) . when the voltage between the bst and sw nodes drops below regulation, a pmos pass transistor connected from v in to bst turns on. the charging current path is from v in to bs t and then to sw. the external circuit should provide enough voltage headroom to facilitate charging. as long as v in is higher than sw significantly , the bootstrap capacitor remains charged. when the hs - fet is on, v in is approximately equal to v sw , so the bootstrap capacitor cannot charge. when the ls - fet is on , v in - v sw reaches its maximum for fast charging ( the c harging path is show n in figure 3 a) . when the hs - fet and ls - fet are both off , v sw is equal to v out , so the difference between v in and v out can c harge the bootstrap capacitor ( the c harging path is shown in figure 3 b) . th e floating driver has its own uvlo protection, with a rising threshold of 2.2v and hysteresis of 150mv. a 20? resistor placed between the sw and bst cap is strongly recommended to reduce sw voltage spikes . v in d1 m1 5v + - u1 + - sw bst r4 c4 l1 c2 v out hs-fet ls-fet 3a: bst charging path when ls - fet is on v in d1 m1 5v + - u1 + - sw bst r4 c4 l1 c2 v out hs-fet ls-fet 3b : bst c harging path when hs - fet and ls - fet are both off figure 3 : internal bootstrap charging circuit start - up and shutdown if both v in and en /sync exceed their appropriate thresholds, the chip starts up. the reference block starts first , generating a stable reference voltage and current, and then the internal regulator is enabled. the regulator provides a stable supply for the remaining circuitries. three events can shut down the chip : en /sync low, v in low, and thermal shutdown. in the shutdown procedure, the signaling path is blocked first to avoid any fault triggering. v comp and the internal supply rail are then pulled down. the floating driver is not subject to this shutdown command. power good (pg) the mpq4420a has a power good (pg) output. pg is the open drain of the mosfet. it should be connect ed to vcc or an other voltage source through a resistor (e.g. : 100k?). in the presence of an input voltage, the mosfet turns on so that pg is pulled low before ss is ready. after v fb reaches 90% x ref, pg is pulled high after a delay ( typically 9 0s ) . when v fb drops to 8 4 % x ref, pg is pulled low . pg is also pulled low if thermal shutdown occurs or if en /sync is pulled low.
mpq4420 a ? 2a , 3 6 v, synchronous , step - down converter mpq4420 a rev . 1.0 www.monolithicpower.com 16 5/24/2016 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. application informat ion setting the output voltage the external resistor divider sets the output voltage (see typical application on page 1). the feedback resistor ( r1 ) also sets the feedback loop band width with the internal compensation capacitor. choose r1 to be around 40 k . r2 can then be calculated with equation (1) : 1 0.792v v r1 r2 out ? = (1) the t - type network is highly recommended when v out is low (see figure 4) . r2 r1 rt 8 fb figure 4 : t - type network rt + r 1 is used to set the loop bandwidth. the higher rt + r1 is , the lower the bandwidth is . t o ensure loop stability, it is strongly recommended to limit the bandwidth below 40khz based on the 410khz default f sw . table 1 lists the recommended t - type resistor value s for common output voltages. table 1 : resistor selection for common output voltages v out (v) r1 (k?) r2 (k?) r t (k?) 3.3 41.2 (1%) 13 (1%) 51 (1%) 5 41.2 (1%) 7.68 (1%) 51 (1%) selecting the inductor use a 1h to 10h inductor with a dc current rating at least 25% higher than the maximum load current for most applications. for the highest effic iency, an inductor with a small dc resistance is recommended . for most designs, the inductance value can be derived from equation (2): out in out 1 in l osc v (v v ) l v if ? = ? (2) where i l is the inductor ripple current. choose the inductor ripple current t o be approximately 30% o f the maximum load current . the maximum inductor peak current can be calculated with equation (3) : 2 i i i l load ) max ( l ? + = (3) use a larger inductor for improved efficiency below 100ma under light - load conditions. v in under - voltage lockout ( uvlo ) setting the mpq4420a has an internal , fix ed, under - voltage lockout (uvlo) threshold . the rising threshold is 3.5 v , while its falling threshold is about 3. 3 v. for application s that need a higher uvlo point, an external resistor divider between en /sync and in can be used to achieve a higher equivalent uvlo threshold (see figure 5 ) . vin en / sync in r 5 500k r 6 figure 5 : adjustable uvlo using en /sync divider t he uvlo threshold can be calculated with equation (4) and equation (5) : en_rising rising v 500k//r6 r5 (1 inuv + = (4) en_falling falling v 500k//r6 r5 (1 inuv + = (5) where v en_rising is 1.4v and v en_falling is 1.25v. w hen selecting r5, ensure that it is large enough to limit the current flow ing into en /sync below 1 5 0 a. selecting the input capacitor the input current to the step - down converter is discontinuous and therefore requires a capacitor to supply ac current to the step - down converter while maintaining the dc input voltage. for best performance , use low esr capacitors. ceramic capacitors with x 5r or x7r dielectrics are recommended because of their low esr and small temperature coefficients.
mpq4420 a ? 2a , 3 6 v, synchronous , step - down converter mpq4420 a rev . 1.0 www.monolithicpower.com 17 5/24/2016 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. f or most application s , a 22f ceramic capacitor is sufficient to maintain the dc input voltage. it is strongly recommended to use another lower value capaci tor (e.g. : 0.1 f) with a small package size (0603) to absorb high - frequency switching noise. place the small er capacitor as close to in and gnd as possible (see pcb layout guidelines on page 18 ). since c1 absorbs the input switching current, it requires an adequate ripple current rating. the rms current in the input capacitor can be estimated with equation (6) : ? ? ? ? ? ? ? ? ? = in out in out load 1 c v v 1 v v i i (6) the wors t - case condition occurs at v in = 2v out , shown in equation (7) : 2 i i load 1 c = (7) for simplification, choose an input capacitor with an rms current rating greater than half of the maximum load current. the input capacitor can be electrolytic, tantalum , or ceramic. when using electrolytic or tantalum capacitors, add a smal l, high - quality ceramic capacitor (e.g. : 1f) placed as close to the ic as possible. when using ceramic capacitors, ensure that they have enough capacitance to provide a sufficient charge to prevent an excessive voltage ripple at input. the input voltage ripple caused by the capacitance can be es timated with equation (8) : load out out in in s in iv v v1 f c1 v v ?? ? = ? ?? ?? (8) selecting the output capacitor the output capacitor (c2) maintains the dc output voltage. ceramic , tantalum, or low esr electrolytic capacitors are recommended . for best results, use low esr c apacitors to keep the output voltage ripple low. the output voltage ripple can be estimated with equation (9) : out out out esr s 1 in s vv 1 v 1r f l v 8 f c2 ?? ?? ? = ? + ?? ?? ?? ?? (9) where l 1 is the inductor value and r esr is the equivalent series resistance (esr) value of the output capacitor. fo r ceramic capacitors, the capacitance dominates the impedance at the switching frequency and causes the majority of the output voltage ripple. for simplification, the output voltage ripple can be estimated with equation (10) : out out out 2 in s1 vv v 1 v 8 f l c2 ?? = ? ?? ?? (10) with tantalum or electrolytic capacitors, the esr dominates the impedance at the switching frequency. for simplification, the output ripple can be approximated with equation (11) : out out out esr in s1 vv v 1 r fl v ?? = ? ?? ?? (11) the characteristics of the output c apacitor also affect the stability of the regulation system. the mpq4420a can be optimized for a wide range of capacitance and esr values. bst resistor and external bst diode a 20 resistor in series with a bst capacitor is recommended to reduce sw voltage spikes . a higher resistance is better for sw spike reduction but compromise s efficiency . an external bst diode can enhance the efficiency of the regulator when the duty cycle is high (>65%). a power supply between 2.5v and 5v can be used to power the exte rnal bootstrap diode . either v cc or vout can be used as the power supply in this circuit (see figure 6 ) . c bst c out l 3 5 bst sw external bst diode 1n4148 vcc/v out vcc 7 v out r bst figure 6 : optional external bootstrap diode to enhance efficiency the recommended external bst diode is in4 148, and the r ecommended bst capacitor value is 0.1f to 1f.
mpq4420 a ? 2a , 3 6 v, synchronous , step - down converter mpq4420 a rev . 1.0 www.monolithicpower.com 18 5/24/2016 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. pc b layout guidelines efficient pcb layout , especially the input capacitor and vcc capacitor placement , is critical for stable operation . for best results, refer to figure 7 and follow the guidelines below . 1. place the ceramic input capacitor as close to in and gnd as possible, especially the small package size (0603) input bypass capacitor . 2. keep the connection of the input capacitor and in as short and wide as possible. 3. place the vcc capacitor to vcc and gnd as close as possible. 4. make the trace length of vcc to the capacitor to gnd as short as possible. 5. use a large ground plane connect ed directly to gnd. 6. add vias near gnd if the bottom layer is the ground plane. 7. route sw and bst away from sensitive analog ar eas such as fb. 8. place the t - type feedback resistor close to the chip to ensure that the trace connect ing to fb is as short as possible. vin vout gnd gnd top layer gnd bottom layer figure 7 : recommended pcb layout
mpq4420 a ? 2a , 3 6 v, synchronous , step - down converter mpq4420 a rev . 1.0 www.monolithicpower.com 19 5/24/2016 mps proprietary information. patent protected . unauthorized photocopy and duplication prohibited. ? 2016 mps. all rights reserved. ty pical application ci rcuit mpq4420a bst sw fb en/sync in vin vout c 4 100nf 22f c2a l1 10h r2 r1 41.2k 13k c1c 0.1f 3.3v/2a gnd 2 6 4 8 3 5 vcc pg c3 0.1f r3 51k 1 7 c1b 10f 10f c1a 1m r5 r4 20 22f c2b r6 100k figure 8: 3.3v output typical application circui t
mpq4420 a ? 2a , 3 6 v, synchronous , step - down converter notice: the information in this document is subject to change without notice. users should warrant and guarantee that third party intellectual property rights are not infringed upon when integrati ng mps products into any application. mps will not assume any legal responsibility for any said applications. mpq4420 a rev . 1.0 www.monolithicpower.com 20 5/24/2016 mps proprietary information. patent protected . unauthorize d photocopy and duplication prohibited. ? 2016 mps. all rights reserved. package information tsot23 - 8 front view note: 1) all dimensions are in millimeters. 2) package length does not include mold flash, protrusion or gate burr. 3) package width does not include interlead flash or protrusion. 4) lead coplanarity (bottom of leads after forming) shall be 0.10 millimeters max. 5) jedec reference is mo-193, variation ba. 6) drawing is not to scale. 7) pin 1 is lower left pin when reading top mark from left to right, (see example top mark) top view recommended land pattern seating plane side view detail ''a'' see detail ''a'' iaaaa pin 1 id see note 7 example top mark

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